The present invention relates to a manufacturing method of semiconductor devices and more particularly to a manufacturing method of semiconductor devices of the type in which interconnection layer groups are arranged in the form of multilayers.
Integrated semiconductor devices become more fine, and the interconnection layer groups are multilayered. Because of this tendency, the upper and lower interconnection layers cross with an insulating layer interposed therebetween, resulting in the crowding of the connection layer group with step portions on the upper portion of the semiconductor device. In order to form such an interconnection layer group by patterning, it is preferable to use an anisotropic etching method, e.g. a reactive ion etching (RIE) process. When such an anisotropic etching method is used, however, the etching progresses only in the direction vertical to the surface of the semiconductor substrate, but does not progress in a lateral direction in parallel with the surface of the semiconductor substrate. Accordingly, when a first level interconnection layer is formed on an insulating layer on a semiconductor substrate and a second level interconnection layer is formed crossing the first level interconnection layer with another insulation layer intervening therebetween, conductive material from forming the second level interconnection layer is left at each side end of the first level interconnection layer between the two crossing portions, and the conductive material left short-circuits the two adjacent second level interconnection layers. This problem will be described with reference to FIGS. 1 and 2. In FIG. 1, numeral 11 designates an insulating oxide layer formed on a semiconductor substrate 10. After a polycrystalline silicon film is formed on the oxide layer 11, this film is subjected to the patterning to form a polycrystalline silicon interconnection layer 12 of a first layer group or first level. Then, the oxide film corresponding to the element region is etched away with a mask of the polycrystalline silicon interconnection layer 12. In the next step, to form a polycrystalline silicon interconnection layer 14 of a second layer group or second level, an insulating layer 13 must be provided between the first and second level interconnection layers 12 and 14. To this end, the first level interconnection layer 12 is oxidized to form an insulating layer 13 of several hundreds A in thickness. FIG. 2 shows a cross section taken along line 2--2 of FIG. 1. After the formation of the insulating film 13, the polycrystalline silicon layer 14 of the second level must be formed by patterning a polycrystalline silicon film provided over the entire surface. As shown in FIG. 2, overhang portions 15 are formed on both the sides of the insulating film 13 when the first level interconnection layer 12 is oxidized. The polycrystalline silicon material coated over the entire surface for forming the second level interconnection layer 14, as a matter of course, enters under the overhang portions 15. In the patterning for the second level interconnection layer 14, as the RIE process is performed, the polycrystalline silicon material 14a under the overhang portions 15 is left, as shown in FIG. 2, without being removed. The residual polycrystalline silicon material 14a short-circuits between the second level interconnection layers 14. In the step of the patterning for forming the second level interconnection layer 14, if the isotropic etching is adapted, the polycrystalline material 14a is not left but use of the isotropic etching is problematic in the RIE method which is essential to the fine patterning.
Accordingly, an object of the present invention is to provide a method of manufacturing semiconductor devices which multilays interconnection layers by the antisotropic etching process, increases the integration density of circuit components, and improves the yield of products.